SSDM2014

TOKYO - Thursday, September 11th 2014 [ME NewsWire]

(BUSINESS WIRE) Toshiba Corporation (TOKYO:6502) today announced the development of Tunneling Field Effect Transistors (TFET) that utilize a new operating principle for ultra-low power MCU. This principle has been applied to the development of two different TFET using a CMOS platform compatible process. By applying each TFET into some circuit blocks, it is possible to achieve significant power reductions in MCUs.

Toshiba presented the TFETs on September 9th and 10th in three presentations at the 2014 Solid State Devices and Materials (SSDM) in Tsukuba, Japan. Two presentations were based on joint research with the Collaborative Research Team Green Nanoelectronics Center (GNC) at the National Institute of Advanced Industrial Science and Technology (AIST).

Rapid demand growth for wireless and mobile devices is driving demand for ultra-low power consumption of LSI. In this situation, innovative devices are strongly required to reduce operation voltage and stand-by leakage current. Tunneling Field Effect Transistor (TFET) utilizing operation novel principle with quantum tunneling effect has attracted much attention to achieve the ultra-low power LSI operation instead of conventional MOSFETs.

Recently, the introduction of new materials, such as III-V compound semiconductors, has been widely investigated for TFET, as they have the potential to realize high performance. However, it is difficult to implement such materials into current CMOS platforms, due to the difficulties resulting from special process utilization.

Toshiba has addressed this problem by optimizing TFET properties for some of key circuit blocks using common CMOS process. This approach enables simple installation of TFET into existing production line. Toshiba has developed two types of Si based TFET, one for logic circuits with ultra-low leakage current and optimized ON current, the other for SRAM circuits with extremely low transistor characteristics variation. Both utilize vertical type tunneling operation to enhance tunneling properties. In addition, the logic TFET employs precisely controlled epitaxial material growth process for tunnel junction formation with carbon and phosphorus doped Si. The Si/SiGe hetero junction has also been comprehensively evaluated to secure optimized configuration. Consequently, the device achieves an ON current two orders of magnitude higher than a Si TFET, which keeps same ultra-low OFF current, both in N and P-type TFET. For the SRAM type TFET development, Toshiba has proposed novel TFET operation architecture which doesn’t need to form a structural tunnel junction. It eliminates process variability and results in significantly suppressed transistor characteristics variation.

Toshiba is going to demonstrate integrating these TFET with conventional MOSFETs in a MCU to reduce total power consumption by one-tenth or more, targeting commercial production and use by 2017.

About Toshiba

Toshiba Corporation, a Fortune 500 company, channels world-class capabilities in advanced electronic and electrical product and systems into five strategic business domains: Energy & Infrastructure, Community Solutions, Healthcare Systems & Services, Electronic Devices & Components, and Lifestyles Products & Services. Guided by the principles of The Basic Commitment of the Toshiba Group, “Committed to People, Committed to the Future”, Toshiba promotes global operations towards securing “Growth Through Creativity and Innovation”, and is contributing to the achievement of a world in which people everywhere live in safe, secure and comfortable society.

Founded in Tokyo in 1875, today’s Toshiba is at the heart of a global network of over 590 consolidated companies employing over 200,000 people worldwide, with annual sales surpassing 6.5 trillion yen (US$63 billion). To find out more about Toshiba, visit www.toshiba.co.jp/index.htm

Contacts

Toshiba Corporation

Semiconductor & Storage Products Company

Megumi Genchi / Kota Yamaji, +81-3-3457-3576

Communication IR Promotion Group

Business Planning Division

semicon-NR-mailbox@ml.toshiba.co.jp

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